Job Responsibilities: SoC Physical Design Engineer
Salary: $20-30 Hour
Company: Apple
Location: Richmond, USA
Educational Requirements: Bachelor Degree
Full Job Description:
At Apple, weighty contemplations have a way to deal with becoming phenomenal things, organizations, and client experiences quickly. Convey excitement and obligation to your work and who can say for sure what you could accomplish. Dynamic, centered people and moving, creative developments are the norm here. People who work here have rethought entire endeavors with all Apple Hardware things. The very excitement for improvement that goes into our things moreover applies to our chips away at supporting our commitment to leave the world better than we found it. Oblige us to help with conveying the accompanying noteworthy Apple thing!
In this significantly obvious work, you will be at risk for executing all out chip plan from netlist to tapeout.
Key Capacities
- Ought to be have a ton of experience with parts of ASIC joining including floorplanning, clock and power scattering, overall sign planning, I/O organizing, and hard IP compromise.
- Experience with standard SoC issues like various voltage and clock spaces, ESD frameworks, going against message block coordination, and pack joint efforts.
- Familiar with an ever-evolving plan approach, progressive arrangement, arranging, timing and real mix.
- Experience planning IP from both internal and outside vendors and have the choice to decide and drive IP essentials in the genuine region is required.
- Experience with huge SoC plans (>20M doorways) with frequencies in overflow of 1GHz using creative sub 45nm progressions.
- An unmistakable perception of data base organization issues is required.
- From a PC supported plan instrument perspective, experience with floorplanning gadgets, P&R streams, overall timing affirmation and genuine arrangement check streams is required.
- Familiar with various connection related plan issues including Plan for Yield and Manufacturability, multi Vt systems and warm Mgt.
Portrayal
• Work with the FE gathering to understand chip designing and drive real points of view without skipping a beat in the arrangement cycle.
• Work with the genuine arrangement gathering to drive draws near and "most famous strategies" to streamline real arrangement work, consider rules and plans, drive execution, and track progress.
• Be a place of union for spot and course, drive the work among spot and course plans, set forth targets and accomplishments, plan short and long stretch work, understand conditions between different spaces like top, STA, block spot and course.
• Resolve plan and stream issues associated with genuine arrangement, perceive likely courses of action, and drive execution.
Guidance and Experience
- Least BS and 2+ significant stretches of significant industry experience
